Precision circuits implemented in metal oxide semiconductor (MOS) integrated circuits include digital-to-analog converters, sample-and-hold circuits and watch circuits having a capacitive tuning section. In each of these circuits, precision capacitors must be switched in and out of the circuit to accurately control voltage levels. The accuracy of such a circuit is impaired if the switching operation changes the amount of charge stored on any of the capacitors which are switched in and out of the circuit. A well-known problem exists whenever an MOS field effect transistor (FET) is used as a switch controlling a precision capacitor, this problem being that the source-to-drain channel of the FET stores charge whenever the FET is turned on. This channel charge is expelled from the channel whenever the FET is turned off. Approximately half of the charge is expelled through the drain, the remainder being expelled through the source so that the amount of charge stored on a capacitor connected to either the source or the drain is increased by one-half of the channel charge stored in the FET whenever the FET is turned off. Accordingly, the voltage across the capacitor varies as the FET is switched on and off in an amount proportional to the capacitance of the capacitor divided by approximately one-half the channel charge stored in the FET.
One prior art solution to this problem is to connect a compensating FET to the node between the capacitor and the switching FET, the compensating FET storing charge in its source-to-drain channel in an amount equal to about one-half the charge stored by the switching FET in its source-to-drain channel. The compensating FET and the switching FET are controlled in complementary fashion so that when the switching FET is turned off, the compensating FET is turned on and absorbs one-half of the channel charge from the switching FET which would otherwise have been stored on the capacitor. Accordingly, the capacitor voltage does not change as much when the switching FET is turned on and off.
This prior art solution suffers from two problems. First, spatial nonuniformities in oxide thickness and gate width across the surface of the integrated circuit chip are usually unavoidable due to imperfections in the process by which MOS circuits are fabricated. Such nonuniformities in oxide thickness and gate width give rise to uncertainty or inaccuracy in the channel charge storing capacity of the compensating transistor. Accordingly, the compensating transistor does not store exactly one-half of the channel charge expelled from the switching FET. Thus, if the channel charge capacity of the compensating FET is greater than one-half the channel charge capacity of the switching FET, the compensating FET may subtract charge from the storage capacitor when it is turned on. On the other hand, if the channel charge capacity of the compensating FET is too small, some of the charge expelled from the switching FET will be added to the storing capacitor. In both cases, the compensation is not exact and therefore the voltage stored across the storing capacitor will vary as the two FETs are turned on and off respectively, a significant disadvantage. The other problem is that the compensating FET only absorbs that charge which is expelled from the one side of the switching FET which is connected to the storage capacitor. The remaining half of the channel charge expelled from the opposite side of the switching FET is not compensated and may enter into other parts of the circuit.